Gyrator hack: Enhancement MOSFET option

Happy Easter to all! (whatever you celebrate, doesn’t matter, it’s always good to have some days off)

I have my preferred gyrator setup which includes a top (depletion) MOSFET IXTP08N100D, which has a unique high VGS(th) which helps improving the performance of the bottom FET, in my case the BSH111BK. The combination of both is superb and they do measure (and sound) superb. The frequency response is flat until 3.4Mhz (-3dB). Yes, a high bandwidth amplifier, so you need to be mindful of this when using high gm/gain valves. I read somewhere people complaining that gyrator “oscillate”. Well they don’t, however they create a high bandwidth amplifier which is therefore prone to oscillate if you don’t take the right measures. If you don’t know what you’re doing, it will oscillate for sure, you have been warned.

Ok, if you can’t get hold of (any) depletion MOSFET as the top device, there is an option, a la Gary Pimms.

The circuit can be tweaked slightly, as can be hacked the PCB (I can show you how if you’re intending to use this circuit)

Here is the design:


The main difference is that D4 provides a stable reference voltage (18V) which ones you subtract the VGS(th) of the top MOSFET (typically 2-5V) then will give you enough headroom to allow the bottom FET to operate under low output capacitance due to higher VDS. This is the common limitation of the cascoded pair of depletion devices. You can’t get more than 2-3V.  As the top device forms a “cascode” with the bottom, it also limits the maximum voltage possible to the drain of the bottom device. The protection zener of the bottom device can be removed to ensure maximum swing. This stage can do 20Vpp easily. C5 provides some filtering to the zener noise, which is very low. I can’t see an issue at the driving levels in place. 

The protection zener (D2) for the top device is needed unless the MOSFET comes with a pair of back to back as some do.

There are multiple options for the top MOSFET. I like the (nearly EOL) STP3NK60ZFP which is a FP TO-220 device, very handy for heatsinks and high voltage and comes with the bonus of the protection zeners. The best option is the AOT1N60 and also the easier to get hold off FQPF2N60C

So, the performance is great. You can get flat response up to 2.1 Mhz. Here is a snapshot with my buffer which limits to 1.5Mhz:



However, my prefered stage can do 3.4Mhz under same conditions!


3 Replies to “Gyrator hack: Enhancement MOSFET option”

  1. I received some feedback from Shane which helped me to spot an error in the schematic:

    “Took me a little while to figure out what he is trying to do.. Change in the circuit to put ~18 volts across T4 using a zener in the reference drop-current source branch. One problem I see right away is what to use for D4. I don’t like D4 and I don’t like C1-R4 either. R4 is 390k and let’s say the plate voltage setting is 100 volts, so CCS current is 100/390k = 256 microamps.
    1N4745A is the 16 volt one. OK zener drop min 15.2, typical 16, max 16.8, test current 15.5 mA, zener impedance 16 ohms@15.5mA.

    And now the problem: zener impedance at Izk (mA) 700 ohms@250uA.
    So the slope of the Zz vs Iz goes from 16 ohms at 15.5mA to 700 ohms at 0.25mA. So they don’t regulate so well down at 1/4mA..
    Zener diodes have leakage and at low current they don’t ac so much like a shunt regulator. I leakage 5uA at 12.2 volts.
    Since the CCS – R4 branch runs a regulated current anyhow, why are we not just using another resistor that drops 16 volts@250uA or 64k ohms?
    Or alternatively why are we running such a low CCS setting when we likely have at least a few mA to spare for this.

    And reading between the lines of his article, the shunt capacities of the MOSFETs are significant enough to want to reduce them.

    Also he moved where C1 connects back into the reference branch from the tube plate (bootstrap capacitor). Value of C1 vs the impedance of where it is connected into the reference branch sets the low-frequency end of the passband of the plate load circuit. He moved it from a 10 Meg ohm impedance point to a 390k ohm impedance point while still using the same value capacitor.
    Chances are T4 and T3 wouldn’t track together at high frequencies without the change. And swapping D4 for a 64k resistor might cause some problems there as well.
    My guess is that one of those 3-terminal ‘adjustable zener reference’ devices would work better for D4. And I think the CCS current needs to be raised, though this causes the value of R4 to be lowered in proportion which starts to become a significant shunting plate load impedance (C1 and R4) to the tube.
    In the original circuit J1 only got 3 volts or so to work with from T3. The change allows J1 to run with more voltage across it than just 3 volts, and then someone also respecified J1 into T4.
    Better? .. I don’t know. I don’t think it’s quite ideal WRT the use of D4 (and no suggested part in the article).”

    I connected by mistake the bootstrap cap (C1) to R4 instead of R6 (10 Meg resistor). I want to clarify some points which may help answering the points above:
    1) The LND150 tempco dependence forces us to run the drain current to below 500uA for best performance, hence the limitation on the CCS. The zener doesn’t like a low current, we know. However, a resistor in place will defeat the VDS voltage fit setting if we want to accommodate a range of anode voltages. If you have a fixed operating point, well you can do it. The resulting impedance may be higher than with a Zener in the node, however there is a cap bypassing the Zener. Some are concerned about the Zener noise, you can use the well-known good for noise BZX55C12V-TAP from VISHAY. Alternatively an RC network (160K +100nF) instead feeding the gate of the top MOSFET. The cap returning to ground – which needs an HV part.
    2) I couldn’t measure any noticeable noise impact from the Zener. You can add a larger cap which reduces the impedance across the zener. Bootstrapping the top MOSFET can help improving slightly the HF response (a la Gary Pimms), but not worth the hassle here.
    3) Depletion FET are perfect for this stage topology when swinging larger volts. Here is where you reach the limitation of the Enhancement FETS and the voltage fixed of the cascode. The depletion FETs help “tracking” the VDS of the lower device given the way is biased the top device. The ‘relative-motion’ of the lower & upper enhancement transistors explains the reduced bandwidth, as well as the headroom-collapse
    4) I tried increasing C5 but not much of a difference is provided by increasing the bootstrap. I’d rather avoid an electrolytic cap here if possible.

    This was just an exercise to get an alternative variation of the gyrator using enhancement devices. In my opinion, I will stick to the IXTP08N100D + BSH111BK which measures much better and sounds really good!
    Hope this helps

  2. Hello Ale,
    Do you happen to have the pspice or ltspice model for the IXYS IXTP08N50D2 or IXYS IXTP08N100D2?
    I have been looking all over the world for it and cant find a sim model. Thanks!!

    1. Hi, no i don’t have am afraid. Just use the DN2540 for basic simulation purposes. You will only get worse HF response and slightly lower power dissipation in the lower FET as the Vds will be lower with the DN2540.

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