Tag: CCS load

Flexible CCS board prototype

I’ve been prototyping a flexible CCS PCB. The intent is to provide a cascoded FET pair with some interesting features:

  1. The lower FET can be multiple devices depending on the choice of reverse capacitance and transconductance. These include jFETs and depletion MOSFETs like the 2SK170, J310, BF862 and of course DN2540. For this purpose several pads are provided for SMD devices as well as TO-92 ones, just like the gyrator PCB. A protection Zener diode between drain and source can be soldered when using low VDSS devices.
  2. There is either a string of trimpot plus a resistor to set the CCS current manually during test given the variance in the FET parameters.  There is also an option to put a fixed resistor.
  3. There is a mu-output connection provided.

The board is very flexible and can be used for multiple purposes:

  1. shunt regulators (including VR valves)
  2. Anode load for phono preamps, drivers, LTPs, etc.
  3. LTP tail CCSs

I’ve been running some tests with excellent results.

If there is interest, I will run a batch of PCB to offer to the DIY community. 

Cheers

Ale

A versatile CCS load

I’m a heavy user of CCS loads. I generally use them to test my valves regardless of using my curve tracer or not. I tried multiple CCS types in the past with good results until I ended up burning one FET or protection zener or whatever due to the abuse of it.

Testing high current loads is not easy at high voltages. The DN2540 is rated at 400V. Not enough. You can use an expensive 01N100D which is another depletion 1KV MOSFET that has a lower Ciss (54pF against 200pF) or you can look at the cheaper enhancement FETs which require a different bias arrangement. If we are looking at modifying the classic cascode self-bias pair, it is a convenient opportunity to improve the VDS bias of the lower FET to improve the frequency response by lowering the Ciss. Remember that in a FET the Ciss is proportional to the VDS. The classic cascode pair has a disadvantage as the lower FET is biased with VDS lower than 1-2V to ensure the upper FET is biased correctly.

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