JFET RIAA Preamp Build (Part II)

I made the following changes to the RIAA stage to improve its accuracy:

  1.  Measured all caps
  2. Adjusted 75uS network to compensate for the capacitor variance and the cascode output impedance
  3. Adjusted 318uS and 3180uS networks to compensate for the capacitor variance

All resistors were adjusted with a pair of 0.1% SMD resistors to avoid series connection to reduce noise level.

As shown below, the response is really good matching at less than 1% for frequencies above 50Hz. the error at low frequency is due to the rumble low pass filter, the hum and the soundcard LF response which introduce a slight distortion at very low frequency in the MLS measurement:

Frequency (Hz) Test (dB) RIAA (dB) Error
                          20 18.80 19.27 2.44%
                        100 13.00 13.09 0.69%
                    1,000 0.00 0.00 0.00%
                  10,000 -13.70 -13.73 0.22%

jfet RIAA test5

RIAA measurement

JFET RIAA preamp project started

20131006-180745.jpgNow is the time to upgrade my current RIAA stage. A bit unorthodox approach for a valve enthusiastic but you will see me now with my hands on sand. A very simple JFET input stage with a shunt cascode pair to drive the passive RIAA network. The final gain stage is an OPA604 with remaining part of the RIAA network. The Op Amp is forced into class A by a nice pair of BC847C forming a CCS.

Given the shunt cascode bipolar is an PNP Darlington formed by 2 BC860C low noise and the CCS has also SMD devices, I started by soldering these into 4 PCB adapters for SOT-23 devices

More to follow…(just a start)