I evolved my previous design here, thanks to the help of Rod Coleman and fruitful discussions with him.
There is an option to improve the design by bootstrapping the top MOSFET to avoid using a bias Zener and allow the bottom device to have a constant VDS. This can be achieved by double bootstrapping the FETs. Here it goes:
Similar design as before. Only difference is that R7 is used to create the bias of T3, and thanks to the bootstrap of C2, the bottom FET (T4) now operates freely regardless the swing. D1 is needed to protect T4. R7need to be adjusted considering the output voltage expected as well as the maximum VDS before D1 starts to conduct.
There is an stability challenge and it can be addressed as Rod Coleman clearly points it out, a “guard ring” :
The other pro trick is the guard ring: this will dramatically reduce problems of dc-drift, if the PCB surface gets contaminated, e.g. when soldered with some old or poor-quality solder. Or damp air, fumes etc. It’s a conductor (pcb trace) around the high-impedance network formed by the 10M resistors. A staggered-pinout version of the TO220 is needed to implement it, as the TO220 is the hotspot for leakage (B+ of drain to the 10MΩ-driven gate!).
If there is a leakage path, it leads only to the guard ring, which is only a few volts away from the intended bias – rather than if the leakage can reach ground or B+, which would drive the circuit crazy. Connect the guard to a low-Z source – the Output in this case.
Anyway – I hope it is useful in some way!
(Rod Coleman)
How well it performs? Here you can see – no guard ring here, just adapted standard PCB for testing purposes:
Not bad at all with 3MHz bandwidth. However, considering the circuit complexity, I much rather stick to the depletion version which performs much better in my view:
Nearly 5.7MHz under same conditions!
Cheers, Ale
